Algorithm/Architecture Co-design of Proportionate-type LMS Adaptive Filters for Sparse System Identification

Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar

This paper investigates the problem of implementing proportionate-type LMS family of algorithms in hardware for sparse adaptive filtering applications especially the network echo cancelation. We derive a re-formulated proportionate type algorithm through algorithm-architecture co-design methodology that can be pipelined and has an efficient architecture for hardware implementation. We study the convergence, steady-state and tracking performances of these re-formulated algorithms for white, color and speech inputs before implementing them in hardware. To the best of our knowledge this is the first attempt to implement proportionate-type algorithms in hardware. We show that Delayed $\mu$-law Proportionate LMS (DMPLMS) algorithm for white input and Delayed Wavelet MPLMS (DWMPLMS) for colored input are the robust VLSI solutions for network echo cancellation where the sparsity of the echo paths can vary with time. We implemented all the designs considering $16$-bit fixed point representation in hardware, synthesized the designs and synthesis results show that DMPLMS algorithm with $\approx25\%$ increase in hardware over conventional DLMS architecture, achieves $3X$ improvement in convergence rate for white input and DWMPLMS algorithm with $\approx58\%$ increase in hardware achieves $15X$ improvement in convergence rate for correlated input conditions.

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