For beyond 2-D CMOS logic, various 3-D integration approaches specially transistor based 3-D integrations such as monolithic 3-D , Skybridge , SN3D  holds most promise. However, such 3D architectures within small form factor increase hotspots and demand careful consideration of thermal management at all levels of integration  as stacked transistors are detached from the substrate (i.e., heat sink). Traditional system level approaches such as liquid cooling , heat spreader , etc. are inadequate for transistor level 3-D integration and have huge cost overhead . In this paper, we investigate the thermal profile for transistor level 3-D integration approaches through finite element based modeling. Additionally, we propose generic physical level heat management features for such transistor level 3-D integration and show their application through detailed thermal modeling and simulations. These features include a thermal junction and heat conducting nano pillar. The heat junction is a specialized junction to extract heat from a selected region in 3-D; it allows heat conduction without interference with the electrical activities of the circuit. In conjunction with the junction, our proposed thermal pillars enable heat dissipation through the substrate; these pillars are analogous to TSVs/Vias, but carry only heat. Such structures are generic and is applicable to any transistor level 3-D integration approaches. We perform 3-D finite element based analysis to capture both static and transient thermal behaviors of 3-D circuits, and show the effectiveness of heat management features. Our simulation results show that without any heat extraction feature, temperature for 3-D integrated circuits increased by almost 100K-200K. However, proposed heat extraction feature is very effective in heat management, reducing temperature from heated area by up to 53%.