Exploration of Performance and Energy Trade-offs for Heterogeneous Multicore Architectures

Anastasiia Butko, Florent Bruguier, David Novo, Abdoulaye Gamatié, Gilles Sassatelli

Energy-efficiency has become a major challenge in modern computer systems. To address this challenge, candidate systems increasingly integrate heterogeneous cores in order to satisfy diverse computation requirements by selecting cores with suitable features. In particular, single-ISA heterogeneous multicore processors such as ARM big.LITTLE have become very attractive since they offer good opportunities in terms of performance and power consumption trade-off. While existing works already showed that this feature can improve system energy-efficiency, further gains are possible by generalizing the principle to higher levels of heterogeneity. The present paper aims to explore these gains by considering single-ISA heterogeneous multicore architectures including three different types of cores. For this purpose, we use the Samsung Exynos Octa 5422 chip as baseline architecture. Then, we model and evaluate Cortex A7, A9, and A15 cores using the gem5 simulation framework coupled to McPAT for power estimation. We demonstrate that varying the level of heterogeneity as well as the different core ratio can lead to up to 2.3x gains in energy efficiency and up to 1.5x in performance. This study further provides insights on the impact of workload nature on performance/energy trade-off and draws recommendations concerning suitable architecture configurations. This contributes in fine to guide future research towards dynamically reconfigurable HSAs in which some cores/clusters can be disabled momentarily so as to optimize certain metrics such as energy efficiency. This is of particular interest when dealing with quality-tunable algorithms in which accuracy can be then traded for compute effort, thereby enabling to use only those cores that provide the best energy-efficiency for the chosen algorithm.

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