At-Speed Logic BIST for IP Cores

B. Cheon, E. Lee, L. -T. Wang, X. Wen, P. Hsu, J. Cho, J. Park, H. Chao, S. Wu

This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported.

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