Design of novel architectures and field programmable gate arrays implementation of two dimensional gaussian surround function

M. C. Hanumantharaju, M. T. Gopalakrishna

A new design and novel architecture suitable for FPGA/ASIC implementation of a 2D Gaussian surround function for image processing application is presented in this paper. The proposed scheme results in enormous savings of memory normally required for 2D Gaussian function implementation. In the present work, the Gaussian symmetric characteristics which quickly falls off toward plus/minus infinity has been used in order to save the memory. The 2D Gaussian function implementation is presented for use in applications such as image enhancement, smoothing, edge detection and filtering etc. The FPGA implementation of the proposed 2D Gaussian function is capable of processing (blurring, smoothing, and convolution) high resolution color pictures of size up to $1600\times1200$ pixels at the real time video rate of 30 frames/sec. The Gaussian design exploited here has been used in the core part of retinex based color image enhancement. Therefore, the design presented produces Gaussian output with three different scales, namely, 16, 64 and 128. The design was coded in Verilog, a popular hardware design language used in industries, conforming to RTL coding guidelines and fits onto a single chip with a gate count utilization of 89,213 gates. Experimental results presented confirms that the proposed method offers a new approach for development of large sized Gaussian pyramid while reducing the on-chip memory utilization.

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