Energy and Latency Aware Application Mapping Algorithm & Optimization for Homogeneous 3D Network on Chip

Vaibhav Jha, Sunny Deol, Mohit Jha, GK Sharma

Energy efficiency is one of the most critical issue in design of System on Chip. In Network On Chip (NoC) based system, energy consumption is influenced dramatically by mapping of Intellectual Property (IP) which affect the performance of the system. In this paper we test the antecedently extant proposed algorithms and introduced a new energy proficient algorithm stand for 3D NoC architecture. In addition a hybrid method has also been implemented using bioinspired optimization (particle swarm optimization) technique. The proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life application such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark and has been compared with the existing algorithm (spiral and crinkle) and has shown better reduction in the communication energy consumption and shows improvement in the performance of the system. Comparing our work with spiral and crinkle, experimental result shows that the average reduction in communication energy consumption is 19% with spiral and 17% with crinkle mapping algorithms, while reduction in communication cost is 24% and 21% whereas reduction in latency is of 24% and 22% with spiral and crinkle. Optimizing our work and the existing methods using bio-inspired technique and having the comparison among them an average energy reduction is found to be of 18% and 24%.

Knowledge Graph



Sign up or login to leave a comment